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ADUM1210BRZ-RL7资料

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Dual-Channel Digital Isolator

ADuM1210

GENERAL DESCRIPTION

The ADuM12101 is a dual-channel, digital isolator based on Analog Devices’ iCoupler® technology. Combining high speed CMOS and monolithic transformer technology, this isolation component provides outstanding performance characteristics superior to alternatives such as optocoupler devices.

By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with optocouplers. The concerns of the typical optocoupler

regarding uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple, iCoupler digital interfaces and stable

performance characteristics. The need for external drivers and other discrete components is eliminated with iCoupler products. Furthermore, iCoupler devices consume one-tenth to one-sixth the power of optocouplers at comparable signal data rates. The ADuM1210 isolator provides two independent isolation channels operable with the supply voltage on either side ranging from 2.7 V to 5.5 V. This provides compatibility with lower voltage systems as well as enabling a voltage translation functionality across the isolation barrier. In addition, the ADuM1210 provides low pulse-width distortion (<3 ns) and tight channel-to-channel matching (<3 ns). Unlike other

optocoupler alternatives, the ADuM1210 isolator has a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions. Furthermore, as an alternative to the ADuM1200 dual-channel, digital isolator that defaults to an output high condition, the ADuM1210’s outputs default to a logic low state when input power is off.

FEATURES

Narrow body, 8-lead SOIC Low power operation 5 V operation

1.1 mA per channel maximum @ 0 Mbps to 2 Mbps 3.7 mA per channel maximum @ 10 Mbps 3 V operation

0.8 mA per channel maximum @ 0 Mbps to 2 Mbps 2.2 mA per channel maximum @ 10 Mbps 3 V/5 V level translation

High temperature operation: 105°C High data rate: dc to 25 Mbps (NRZ) Precise timing characteristics

3 ns maximum pulse width distortion

3 ns maximum channel-to-channel matching High common-mode transient immunity: >25 kV/μs Safety and regulatory approvals UL recognition

2500 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A VDE certificate of conformity

DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01

DIN EN 60950 (VDE 0805): 2001-12; DIN EN 60950: 2000 VIORM = 560 V peak

APPLICATIONS

Size-critical multichannel isolation SPI® interface/data converter isolation

RS-232/RS-422/RS-485 transceiver isolation Digital field bus isolation

Protected by U.S. Patents 5,952,849; 6,873,065; and other pending patents.

FUNCTIONAL BLOCK DIAGRAM

VDD11VIA2VIB3GND14ENCODEENCODEDECODEDECODE8765VDD2VOAVOBGND205459-001

Figure 1.

Rev. A

nformation furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

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ADuM1210

Recommended Operating Conditions....................................10 Absolute Maximum Ratings.........................................................11 ESD Caution................................................................................11 Pin Configuration and Function Descriptions...........................12 Typical Performance Characteristics...........................................13 Application Information................................................................14 PC Board Layout........................................................................14 Propagation Delay-Related Parameters...................................14 DC Correctness and Magnetic Field Immunity...........................14 Power Consumption..................................................................15 Outline Dimensions.......................................................................16 Ordering Guide..........................................................................16

TABLE OF CONTENTS

Features..............................................................................................1 Applications.......................................................................................1 General Description.........................................................................1 Functional Block Diagram..............................................................1 Revision History...............................................................................2 Specifications.....................................................................................3 Electrical Characteristics—5 V Operation................................3 Electrical Characteristics—3 V Operation................................5 Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V

Operation.......................................................................................7 Package Characteristics...............................................................9 Regulatory Information...............................................................9 Insulation and Safety-Related Specifications............................9 DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation

Characteristics............................................................................10

REVISION HISTORY

2/06—Rev. 0 to Rev. A

Updated Format..................................................................Universal Added Note 1....................................................................................1 Changes to Absolute Maximum Ratings.....................................11 Changes to DC Correctness and Magnetic Field

Immunity Section...........................................................................14 7/05—Revision 0: Initial Version

Rev. A | Page 2 of 16

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ADuM1210

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All minimum/maximum specifications

apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. Table 1.

Parameter

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent Output Supply Current, per Channel, Quiescent Total Supply Current, Two Channels1

DC to 2 Mbps

VDD1 Supply Current VDD2 Supply Current 10 Mbps

VDD1 Supply Current VDD2 Supply Current Input Currents

Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages

Logic Low Output Voltages

SWITCHING SPECIFICATIONS Minimum Pulse Width2Maximum Data Rate3Propagation Delay4

Pulse-Width Distortion, |tPLH − tPHL|4

Change vs. Temperature Propagation Delay Skew5

Channel-to-Channel Matching, Codirectional Channels6

Channel-to-Channel Matching, Opposing- Directional Channels6

Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output7

Common-Mode Transient Immunity at Logic Low Output7Refresh Rate

Input Dynamic Supply Current, per Channel8Output Dynamic Supply Current, per Channel8

Symbol

IDDI (Q) IDDO (Q)

IDD1 (Q)IDD2 (Q)

IDD1 (10) IDD2 (10) IIA, IIB VIH VIL VOAH VOBHVOAL VOBL PW

tPHL, tPLH PWD tPSKtPSKCDtPSKODtR/tF |CMH| |CML| fr IDDI (D)IDDO (D)

Min −10 0.7 VDD1, VDD2

VDD1/

VDD2 − 0.1 VDD1/

VDD2 − 0.5 10 20 25

Typ Max Unit 0.50 0.60 mA 0.19 0.25 mA 1.1 1.4 mA 0.5 0.8 mA 4.3 5.5 mA 1.3 2.0 mA +0.01 +10 μA

V 5.0 4.8 0.0 0.04 0.2 5 2.5 35

0.3 VDD1, VDD2 0.1 0.1 0.4 100 50 3 15 3 15

V V V V V V ns Mbps ns ns ps/°C ns ns ns ns kV/μs

Test Conditions

DC to 1 MHz logic signal freq. DC to 1 MHz logic signal freq.

5 MHz logic signal freq. 5 MHz logic signal freq. 0 ≤ VIA, VIB ≤ VDD1 or VDD2

IOx = −20 μA, VIx = VIxH IOx = −4 mA, VIx = VIxH IOx = 20 μA, VIx = VIxL IOx = 400 μA, VIx = VIxL IOx = 4 mA, VIx = VIxL

CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels

CL = 15 pF, CMOS signal levels VIx = VDD1, VDD2, VCM = 1000 V, transient magnitude = 800 V

25 35 kV/μs VIx = 0 V, VCM = 1000 V,

transient magnitude = 800 V

1.2 Mbps 0.19 mA/Mbps 0.05 mA/Mbps

Rev. A | Page 3 of 16

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ADuM1210

Supply current values are for both channels running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 4 through Figure 6 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 7 through Figure 8 for total IDD1 and IDD2 supply currents as a function of data rate. 2

The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed. 3

The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed. 4

tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5

tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 4 through Figure 6 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate.

Rev. A | Page 4 of 16

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ADuM1210

ELECTRICAL CHARACTERISTICS—3 V OPERATION

All voltages are relative to their respective ground. 2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V. Table 2.

Parameter

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent Output Supply Current, per Channel, Quiescent Total Supply Current, Two Channels1DC to 2 Mbps

VDD1 Supply Current VDD2 Supply Current 10 Mbps

VDD1 Supply Current VDD2 Supply Current Input Currents

Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages

Logic Low Output Voltages

SWITCHING SPECIFICATIONS Minimum Pulse Width2Maximum Data Rate3Propagation Delay4

Pulse-Width Distortion, |tPLH − tPHL|4

Change vs. Temperature Propagation Delay Skew5

Channel-to-Channel Matching, Codirectional Channels6

Channel-to-Channel Matching, Opposing- Directional Channels6

Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output7

Common-Mode Transient Immunity at Logic Low Output7Refresh Rate

Input Dynamic Supply Current, per Channel8Output Dynamic Supply Current, per Channel8

Symbol IDDI (Q)IDDO (Q)

IDD1 (Q)IDD2 (Q)

IDD1 (10) IDD2 (10) IIA, IIB VIH VIL VOAH VOBHVOAL VOBL PW

tPHL, tPLH PWD tPSK tPSKCD tPSKOD tR/tF |CMH| |CML| fr IDDI (D)IDDO (D)

Min −10 0.7 VDD1, VDD2 VDD1/ VDD2 − 0.1 VDD1/ VDD2 − 0.5 10 20 25

Typ Max 0.26 0.35 0.11 0.20 0.6 1.0 0.2 0.6 2.2 3.4 0.7 1.1 +0.01 +10 3.0 2.8 0.0 0.04 0.2 5 3.0 35

0.3 VDD1, VDD2 0.1 0.1 0.4 100 60 3 22 3 22

Unit mA mA mA mA mA mA μA

Test Conditions

DC to 1 MHz logic signal freq. DC to 1 MHz logic signal freq.

5 MHz logic signal freq. 5 MHz logic signal freq. 0 ≤ VIA, VIB, ≤ VDD1 or VDD2

V V V V V V ns Mbps ns ns ps/°C ns ns ns ns kV/μs

IOx = −20 μA, VIx = VIxHIOx = −4 mA, VIx = VIxH

IOx = 20 μA, VIx = VIxLIOx = 400 μA, VIx = VIxL IOx = 4 mA, VIx = VIxL

CL = 15 pF, CMOS signal levels VIx = VDD1, VDD2, VCM = 1000 V, transient magnitude = 800 V

25 35 kV/μs VIx = 0 V, VCM = 1000 V,

transient magnitude = 800 V

1.1 Mbps 0.10 mA/Mbps 0.03 mA/Mbps

Rev. A | Page 5 of 16

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ADuM1210

The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 4 through Figure 6 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 7 and Figure 8 for total IDD1 and IDD2 supply currents as a function of data rate. 2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4

Rev. A | Page 6 of 16

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ADuM1210

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION

All voltages are relative to their respective ground. 5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V. 3 V/5 V operation: 2.7 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5.0 V; or VDD1 = 5.0 V, VDD2 = 3.0 V. Table 3.

Parameter

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent 5 V/3 V Operation 3 V/5 V Operation

Output Supply Current, per Channel, Quiescent 5 V/3 V Operation 3 V/5 V Operation

Total Supply Current, Two Channels1DC to 2 Mbps

VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation 10 Mbps

VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation Input Currents

Logic High Input Threshold Logic Low Input Threshold 5 V/3 V Operation 3 V/5 V Operation

Logic High Output Voltages

Logic Low Output Voltages

SWITCHING SPECIFICATIONS Minimum Pulse Width2Maximum Data Rate3Propagation Delay4

Pulse-Width Distortion, |tPLH − tPHL|4

Change vs. Temperature Propagation Delay Skew5

Channel-to-Channel Matching, Codirectional Channels6

Channel-to-Channel Matching, Opposing- Directional Channels6

Symbol

IDDI (Q)

IDDO (Q)

IDD1 (Q)

IDD2 (Q)

IDD1 (10)

IDD2 (10)

IIA, IIB VIH VIL

VOAH, VOBH VOAL, VOBL PW

tPHL, tPLH PWD tPSK tPSKCD tPSKOD

Min −10 0.7 VDD1, VDD2 0.8 0.4 VDD1/ VDD2 − 0.1 VDD1/ VDD2 − 0.5 10 15

Typ Max Unit Test Conditions mA 0.50 0.6 mA 0.26 0.35 mA mA 0.11 0.20 mA 0.19 0.25 mA 1.1 1.4 mA DC to 1 MHz logic signal freq. 0.6 1.0 mA DC to 1 MHz logic signal freq. 0.2 0.6 mA DC to 1 MHz logic signal freq. 0.5 0.8 mA DC to 1 MHz logic signal freq. 4.3 5.5 mA 5 MHz logic signal freq. 2.2 3.4 mA 5 MHz logic signal freq. 0.7 1.1 mA 5 MHz logic signal freq. 1.3 2.0 mA 5 MHz logic signal freq. +0.01 +10 μA 0 ≤ VIA, VIB ≤ VDD1 or VDD2 V VDD1, VDD2 VDD1, VDD2 − 0.2 0.0 0.04 0.2 5

0.3 VDD1, V VDD2 V V

V IOx = −20 μA, VIx = VIxH V IOx = −4 mA, VIx = VIxH0.1 0.1 0.4 100 55 3 22 3 22

V V V ns Mbps ns ns ps/°C ns ns ns

IOx = 20 μA, VIx = VIxLIOx = 400 μA, VIx = VIxLIOx = 4 mA, VIx = VIxL

Rev. A | Page 7 of 16

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ADuM1210

Symbol tR/tf

|CMH| |CML| fr IDDI (D)

IDDO (D)

Min 25 25

Typ 3.0 2.5 35 35 1.2 1.1 0.19 0.10 0.03 0.05

Max

Test Conditions

CL = 15 pF, CMOS signal levels

VIx = VDD1, VDD2, VCM = 1000 V, transient magnitude = 800 V

kV/μs VIx = 0 V, VCM = 1000 V,

transient magnitude = 800 V

Mbps Mbps mA/Mbps mA/Mbps mA/Mbps mA/Mbps Unit ns ns kV/μs

Parameter

Output Rise/Fall Time (10% to 90%) 5 V/3 V Operation 3 V/5 V Operation

Common-Mode Transient Immunity at Logic High Output7

Common-Mode Transient Immunity at Logic Low Output7Refresh Rate

5 V/3 V Operation 3 V/5 V Operation

Input Dynamic Supply Current, per Channel8

5 V/3 V Operation 3 V/5 V Operation

Output Dynamic Supply Current, per Channel8

5 V/3 V Operation 3 V/5 V Operation

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4

Rev. A | Page 8 of 16

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ADuM1210

PACKAGE CHARACTERISTICS

Table 4.

Parameter

Resistance (Input-to-Output)1Capacitance (Input-to-Output)1Input Capacitance

IC Junction-to-Case Thermal Resistance, Side 1 IC Junction-to-Case Thermal Resistance, Side 2

Symbol RI-O CI-O CIθJCIθJCO

Min Typ 1012 1.0 4.0 46

Max

Unit Ω pF pF °C/W °C/W Test Conditions

f = 1 MHz

Thermocouple located at center of package underside

The device is considered a 2-terminal device; Pin 1, Pin 2, Pin 3, and Pin 4 are shorted together, and Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together.

REGULATORY INFORMATION

The ADuM1210 is approved by the following organizations: Table 5.

Recognized under 1577 Component Recognition Program1

2500 V rms isolation voltage

CSA

Approved under CSA Component Acceptance Notice #5A

VDE

Certified according to

DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-012Basic insulation, 560 V peak

Complies with DIN EN 60747-5-2 (VDE 0884

Part 2):2003-01, DIN EN 60950 (VDE 0805):2001-12; EN 60950:2000, Reinforced insulation, 560 V peak

File 2471900-4880-0001

File E214100

File 205078

In accordance with UL1577, each ADuM1210 is proof-tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 5 μA). In accordance with DIN EN 60747-5-2, each ADuM1210 is proof-tested by applying an insulation test voltage ≥ 1050 V peak for 1 second (partial discharge detection limit = 5 pC).

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 6.

Parameter

Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage)

Minimum Internal Gap (Internal Clearance)

Tracking Resistance (Comparative Tracking Index) Isolation Group

Symbol

L(I01) L(I02) CTI

Value 2500 4.90 min 4.01 min 0.017 min >175 IIIa

Unit V rms mm mm mm V

Conditions

1-minute duration

Measured from input terminals to output terminals, shortest distance through air

Measured from input terminals to output terminals, shortest distance path along body Insulation distance through insulation DIN IEC 112/VDE 0303 Part 1

Material Group (DIN VDE 0110, 1/89, Table 1)

Rev. A | Page 9 of 16

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ADuM1210

DIN EN 60747-5-2 (VDE 0884 PART 2) INSULATION CHARACTERISTICS

Table 7.

Description Symbol Characteristic Unit Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms I−IV For Rated Mains Voltage ≤ 300 V rms I−III For Rated Mains Voltage ≤ 400 V rms I−II Climatic Classification 40/105/21 Pollution Degree (DIN VDE 0110, Table 1) 2 Maximum Working Insulation Voltage VIORM 560 V peak Input-to-Output Test Voltage, Method b1 VPR 1050 V peak VIORM × 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC Input-to-Output Test Voltage, Method a VPR After Environmental Tests Subgroup 1 VIORM × 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC 896 V peak After Input and/or Safety Test Subgroup 2/3 VIORM × 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC 672 V peak Highest Allowable Overvoltage (Transient Overvoltage, tTR = 10 sec) VTR 4000 V peak Safety-Limiting Values (maximum value allowed in the event of a failure; also see Figure 2) Case Temperature TS 150 °C Side 1 Current IS1 160 mA Side 2 Current IS2 170 mA Insulation Resistance at TS, VIO = 500 V RS >109 Ω

Note that the “*” marking on the package denotes DIN EN 60747-5-2 approval for a 560 V peak working voltage.

This isolator is suitable for basic isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits.

200180SAFETY-LIMITING CURRENT (mA)RECOMMENDED OPERATING CONDITIONS

Table 8.

SIDE #1SIDE #216014012010080604020050100150CASE TEMPERATURE (°C)20005459-002Parameter

Operating Temperature Supply Voltages1

Input Signal Rise and Fall Times

Symbol TA

VDD1, VDD2 Min −40 2.7 Max +105 5.5 1.0 Unit °C V ms

All voltages are relative to their respective ground. See the DC Correctness and

Magnetic Field Immunity section for information on immunity to external magnetic fields.

Figure 2. Thermal Derating Curve, Dependence of Safety Limiting Values

on Case Temperature, per DIN EN 60747-5-2

Rev. A | Page 10 of 16

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ADuM1210

ABSOLUTE MAXIMUM RATINGS

Ambient temperature = 25°C, unless otherwise noted. Table 9.

Parameter

Storage Temperature

Ambient Operating Temperature Supply Voltages1Input Voltage1Output Voltage1

Average Output Current, per Pin2Common-Mode Transients3

All voltages are relative to their respective ground.

See Figure 2 for maximum rated current values for various temperatures. 3

Refers to common-mode transients across the insulation barrier. Common-mode transients exceeding the Absolute Maximum Rating may cause latch-up or permanent damage.

Symbol TST TA

VDD1, VDD2 VIA, VIBVOA, VOBIO

CML, CMHMin Max −55 150 −40 105 −0.5 7.0 −0.5 VDDI + 0.5 −0.5 VDDO + 0.5 −35 35

−100 +100 Unit °C °C V V V mA

kV/μs

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; Functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Table 10. ADuM1210 Truth Table (Positive Logic)

VIA Input H L H L X X

VIB Input H L L H X X

VDD1 State Powered Powered Powered Powered Unpowered Powered

VDD2 State Powered Powered Powered Powered Powered Unpowered

VOA Output H L H L L

Indeterminate

VOB Output H L L H L

Indeterminate

Notes

Outputs return to the input state within 1 μs of VDDI power restoration.

Outputs return to the input state within 1 μs of VDDO power restoration.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. A | Page 11 of 16

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ADuM1210

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VDD11VIA2VIB3GND14ADuM1210TOP VIEW(Not to Scale)8765VDD2VOAVOBGND205459-003

Figure 3. Pin Configuration

Table 11. Pin Function Descriptions

Pin No. 1 2 3 4 5 6 7 8

Mnemonic VDD1 VIA VIB GND1 GND2 VOB VOA VDD2

Description

Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V. Logic Input A. Logic Input B.

Ground 1. Ground reference for isolator Side 1. Ground 2. Ground reference for isolator Side 2. Logic Output B. Logic Output A.

Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.

Rev. A | Page 12 of 16

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TYPICAL PERFORMANCE CHARACTERISTICS

108)Am( LE6)ANmN( ATHNCE/TN4RREURR5VCUC3V204010203000-95DATA RATE (Mbps)450

Figure 4. Typical Input Supply Current per Channel vs.

Data Rate for 5 V and 3 V Operation

4)3Am( L)EANmN( AH2TNCE/TRNRER5VUCRUC13V05010203000-95DATA RATE (Mbps)450

Figure 5. Typical Output Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation (No Output Load)

)3Am( LEN5VNAH2C/TNERRUC13V06010203000-95DATA RATE (Mbps)450

Figure 6. Typical Output Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation (15 pF Output Load)

Rev. A | Page 13 of 16

ADuM1210

2015105V53V07010203000-95DATA RATE (Mbps)450

Figure 7. Typical ADuM1210 VDD1 Supply Current vs.

Data Rate for 5 V and 3 V Operation

4325V3V108010203000-95DATA RATE (Mbps)450

Figure 8. Typical VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation

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ADuM1210

The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, therefore establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by

APPLICATION INFORMATION

PC BOARD LAYOUT

The ADuM1210 digital isolator requires no external interface circuitry for the logic interfaces. Power supply bypassing is

strongly recommended at the input and output supply pins. The capacitor value should be between 0.01 μF and 0.1 μF. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm.

V=(−dβ/dt)∑Πrn2;n=1,2,...N where:

β is the magnetic flux density (gauss).

N is the number of turns in the receiving coil.

rn is the radius of the nth turn in the receiving coil (cm). Given the geometry of the receiving coil in the ADuM1210 and an imposed requirement that the induced voltage is at most 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated, as shown in Figure 10.

100PROPAGATION DELAY-RELATED PARAMETERS

Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The propagation delay to a logic low output can differ from the propagation delay to a logic high output.

INPUT (VIX)50%tPLHOUTPUT (VOX)tPHL50%05459-009

MAXIMUM ALLOWABLE MAGNETIC FLUXDENSITY (kgauss)Figure 9. Propagation Delay Parameters

Pulse-width distortion is the maximum difference between the two propagation delay values and is an indication of how accurately the input signal’s timing is preserved.

Channel-to-channel matching refers to the maximum amount that the propagation delay differs between channels within a single ADuM1210 component.

Propagation delay skew refers to the maximum amount that the propagation delay differs between multiple ADuM120x components operating under the same conditions.

1010.10.0110k1M10M100kMAGNETIC FIELD FREQUENCY (Hz)100M05459-0100.0011kDC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is therefore either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions of more than 2 μs at the input, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses for more than about 5 μs, the input side is

assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Table 10) by the watchdog timer circuit.

The ADuM1210 is extremely immune to external magnetic fields. The limitation on the ADuM1210’s magnetic field immunity is set by the condition in which induced voltage in the transformer’s receiving coil is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which this can occur. The 3 V operating condition of the ADuM1210 is examined because it represents the most susceptible mode of operation.

Figure 10. Maximum Allowable External Magnetic Flux Density

For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse (and had the worst-case polarity), it would reduce the received pulse from >1.0 V to 0.75 V—still well above the 0.5 V sensing threshold of the decoder.

The preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the ADuM1210 transformers. Figure 11 expresses these allowable current magnitudes as a function of frequency for selected distances. As seen, the ADuM1210 is extremely immune and can be affected only by extremely large currents operated at high frequency and very close to the component. For the 1 MHz example, one would have to place a 0.5 kA current 5 mm away from the ADuM1210 to affect the component’s operation.

Rev. A | Page 14 of 16

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1000MAXIMUM ALLOWABLE CURRENT (kA)ADuM1210

DISTANCE = 1m100POWER CONSUMPTION

The supply current at a given channel of the ADuM1210 isolator is a function of the supply voltage, the channel’s data rate, and the channel’s output load.

10DISTANCE = 100mm1DISTANCE = 5mm0.1For each input channel, the supply current is given by

IDDI = IDDI (Q)

IDDI = IDDI (D) × (2f – fr) + IDDI (Q)

f ≤ 0.5frf > 0.5fr

for each output channel, the supply current is given by

IDDO = IDDO (Q)

05459-0110.011k10k100k1M10M100MMAGNETIC FIELD FREQUENCY (Hz)f ≤ 0.5fr

Figure 11. Maximum Allowable Current for Various

Current-to-ADuM1210 Spacings

IDDO = (IDDO (D) + (0.5 × 10−3) × CLVDDO) × (2f – fr) + IDDO (Q)

f > 0.5fr

where:

IDDI (D), IDDO (D) are the input and output dynamic supply currents

per channel (mA/Mbps).

CL is the output load capacitance (pF). VDDO is the output supply voltage (V).

f is the input logic signal frequency (MHz, half of the input data rate, NRZ signaling).

fr is the input stage refresh rate (Mbps).

IDDI (Q), IDDO (Q) are the specified input and output quiescent supply currents (mA).

To calculate the total IDD1 and IDD2 supply current, the supply currents for each input and output channel corresponding to IDD1 and IDD2 are calculated and totaled. Figure 4 and Figure 5 provide per-channel supply currents as a function of data rate for an unloaded output condition. Figure 6 provides per-channel supply current as a function of data rate for a 15 pF output condition. Figure 7 and Figure 8 provide total IDD1 and IDD2 supply current as a function of data rate.

Note that at combinations of strong magnetic fields and high frequencies, any loops formed by printed circuit board traces could induce sufficiently large error voltages to trigger the threshold of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.

Rev. A | Page 15 of 16

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ADuM1210

OUTLINE DIMENSIONS

5.00 (0.1968)4.80 (0.1890)8544.00 (0.1574)3.80 (0.1497)16.20 (0.2440)5.80 (0.2284)1.27 (0.0500)BSC0.25 (0.0098)0.10 (0.0040)1.75 (0.0688)1.35 (0.0532)0.50 (0.0196)× 45°0.25 (0.0099)0.51 (0.0201)COPLANARITYSEATING0.31 (0.0122)0.10PLANE8°0.25 (0.0098)0°1.27 (0.0500)0.40 (0.0157)0.17 (0.0067)COMPLIANT TO JEDEC STANDARDS MS-012-AACONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 12. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model

ADuM1210BRZ2

ADuM1210BRZ-RL72

Number of Inputs, VDD1 Side 2 2 Number of Inputs, VDD2 Side 0 0 Maximum Data Rate (Mbps) 10 10 Maximum Propagation Delay, 5 V (ns) 50 50 Maximum Pulse-Width Distortion (ns) 3 3

Temperature Range (°C) −40 to +105 −40 to +105 Package Option1R-8 R-8

R-8 = 8-lead, narrow body SOIC. Z = Pb-free part.

Rev. A | Page 16 of 16

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