元器件交易网www.cecb2b.com TLC548C, TLC548I, TLC549C, TLC549I8-BIT ANALOG-TO-DIGITAL CONVERTERSWITH SERIAL CONTROLSLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 1996DMicroprocessor Peripheral or StandaloneDDDDDDDDDDD DOperation8-Bit Resolution A/D ConverterDifferential Reference Input VoltagesConversion Time...17 µs MaxTotal Access and Conversion Cycles PerSecond– TLC548...up to 45500– TLC549...up to 40000On-Chip Software-ControllableSample-and-Hold FunctionTotal Unadjusted Error...±0.5 LSB Max4-MHz Typical Internal System ClockWide Supply Range...3Vto6VLow Power Consumption...15mWMaxIdeal for Cost-Effective, High-PerformanceApplications including Battery-OperatedPortable InstrumentationPinout and Control Signals CompatibleWith the TLC540 and TLC545 8-Bit A/DConverters and with the TLC1540 10-BitA/D ConverterCMOS TechnologyD OR P PACKAGE(TOP VIEW)REF+ANALOG INREF–GND12348765VCCI/O CLOCKDATA OUTCSdescriptionThe TLC548 and TLC549 are CMOS analog-to-digital converter (ADC) integrated circuits built around an 8-bitswitched-capacitor successive-approximation ADC. These devices are designed for serial interface with amicroprocessor or peripheral through a 3-state data output and an analog input. The TLC548 and TLC549 useonly the input/output clock (I/O CLOCK) input along with the chip select (CS) input for data control. Themaximum I/O CLOCK input frequency of the TLC548 is 2.048 MHz, and the I/O CLOCK input frequency of theTLC549 is specified up to 1.1 MHz.AVAILABLE OPTIONSPACKAGETA0°C to 70°C–40°C to 85°CSMALL OUTLINE(D)TLC548CDTLC549CDTLC548IDTLC549IDPLASTIC DIP(P)TLC548CPTLC549CPTLC548IPTLC549IPPlease be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.Copyright © 1996, Texas Instruments IncorporatedPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•1元器件交易网www.cecb2b.comSLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 1996TLC548C, TLC548I, TLC549C, TLC549I8-BIT ANALOG-TO-DIGITAL CONVERTERSWITH SERIAL CONTROLdescription (continued) Operation of the TLC548 and the TLC549 is very similar to that of the more complex TLC540 and TLC541devices; however, the TLC548 and TLC549 provide an on-chip system clock that operates typically at 4 MHzand requires no external components. The on-chip system clock allows internal device operation to proceedindependently of serial input/output data timing and permits manipulation of the TLC548 and TLC549 as desiredfor a wide range of software and hardware requirements. The I/O CLOCK together with the internal system clockallow high-speed data transfer and conversion rates of 45500 conversions per second for the TLC548, and40000 conversions per second for the TLC549.Additional TLC548 and TLC549 features include versatile control logic, an on-chip sample-and-hold circuit thatcan operate automatically or under microprocessor control, and a high-speed converter with differentialhigh-impedance reference voltage inputs that ease ratiometric conversion, scaling, and circuit isolation fromlogic and supply noises. Design of the totally switched-capacitor successive-approximation converter circuitallows conversion with a maximum total error of ±0.5 least significant bit (LSB) in less than 17 µs.The TLC548C and TLC549C are characterized for operation from 0°C to 70°C. The TLC548I and TLC549I arecharacterized for operation from –40°C to 85°C.functional block diagramREF+REF–132SampleandHold8-BitAnalog-toDigitalConverter(Switched-Capacitors)8OutputDataRegiser848-to-1 DataSelectorandDriverANALOG IN6DATAOUTInternalSystemClockCSI/O CLOCK57ControlLogic andOutput Countertypical equivalent inputsINPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE1 kΩ TYPANALOG INCi = 60 pF TYP(equivalent inputcapacitance)ANALOG IN5 MΩ TYPINPUT CIRCUIT IMPEDANCE DURING HOLD MODE2POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com TLC548C, TLC548I, TLC549C, TLC549I8-BIT ANALOG-TO-DIGITAL CONVERTERSWITH SERIAL CONTROLSLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 1996operating sequence1I/OCLOCKtsu(CS)CStwH(CS)DATAOUTHi-Z StateA7A6A5A4A3A2A1A0A7Previous Conversion Data AMSBLSB(see Note B)tenMSBtenMSBB7B6B5B4B3B2B1B0B7Conversion Data BLSBMSBHi-Z State2345678Don’tCare12345678AccessCycle BSampleCycle Btconv(see Note A)tsu(CS)AccessCycle CSampleCycle CNOTES:A.The conversion cycle, which requires 36 internal system clock periods (17 µs maximum), is initiated with the eighth I/O clock pulsetrailing edge after CS goes low for the channel whose address exists in memory at the time.B.The most significant bit (A7) is automatically placed on the DATA OUT bus after CS is brought low. The remaining seven bits (A6–A0)are clocked out on the first seven I/O clock falling edges. B7–B0 follows in the same manner.absolute maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 VInput voltage range at any input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 VOutput voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 VPeak input current range (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mAPeak total input current range (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 mAOperating free-air temperature range, TA (see Note 2): TLC548C, TLC549C . . . . . . . . . . . . . 0°C to 70°CTLC548I, TLC549I . . . . . . . . . . . . –40°C to 85°CStorage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°CNOTES:1.All voltage values are with respect to the network ground terminal with the REF– and GND terminals connected together, unlessotherwise noted.2.The D package is not recommended below –40°C.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•3元器件交易网www.cecb2b.comSLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 1996TLC548C, TLC548I, TLC549C, TLC549I8-BIT ANALOG-TO-DIGITAL CONVERTERSWITH SERIAL CONTROLrecommended operating conditionsTLC548MINSupply voltage, VCCPositive reference voltage, Vref+ (see Note 3)Negative reference voltage, Vref– (see Note 3)Differential reference voltage, Vref+, Vref– (see Note 3)Analog input voltage (see Note 3)High-level control input voltage, VIH (for VCC = 4.75 V to 5.5 V)Low-level control input voltage, VIL (for VCC = 4.75 V to 5.5 V)Input/output clock frequency, fclock(I/O) (for VCC = 4.75 V to 5.5 V)Input/output clock high, twH(I/O) (for VCC = 4.75 V to 5.5 V)Input/output clock low, twL(I/O) (for VCC = 4.75 V to 5.5 V)Input/output clock transition time, tt(I/O) (for VCC = 4.75 V to 5.5 V) (see Note 4 and Operating Sequence)Duration of CS input high state during conversion, twH(CS)(for VCC = 4.75 V to 5.5 V) (see Operating Sequence)Setup time, CS low before first I/O CLOCK, tsu(CS) (for VCC = 4.75 V to 5.5 V) (see Note 5)TLC548C, TLC549CTLC548I, TLC549I32.5–0.11020.80200200100171.40–407085171.40–4070852.0480404404100NOM5MAX6MIN32.5–0.11020.81.1TLC549NOM5MAX6UNITVVVVVVVMHznsnsnsµsµs°C VCCVCC+0.102.5VCCVCC+0.2VCCVCCVCC+0.102.5VCCVCC+0.2VCCNOTES:3.Analog input voltages greater than that applied to REF+ convert to all ones (11111111), while input voltages less than that appliedto REF– convert to all zeros (00000000). For proper operation, the positive reference voltage Vref+, must be at least 1 V greater thanthe negative reference voltage, Vref–. In addition, unadjusted errors may increase as the differential reference voltage, Vref+ – Vref–,falls below 4.75 V.4.This is the time required for the I/O CLOCK input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinityof normal room temperature, the devices function with input clock transition time as slow as 2 µs for remote data acquisitionapplications in which the sensor and the ADC are placed several feet away from the controlling microprocessor.5.To minimize errors caused by noise at the CS input, the internal circuitry waits for two rising edges and one falling edge of internalsystem clock after CS↓ before responding to control input signals. This CS setup time is given by the ten and tsu(CS) specifications.4POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com TLC548C, TLC548I, TLC549C, TLC549I8-BIT ANALOG-TO-DIGITAL CONVERTERSWITH SERIAL CONTROLSLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 1996electrical characteristics over recommended operating free-air temperature range,VCC = Vref+ = 4.75 V to 5.5 V, fclock(I/O) = 2.048 MHz for TLC548 or 1.1 MHz for TLC549 (unless otherwise noted)PARAMETERVOHVOLIOZIIHIILII()I(on)ICCICC + IrefCiHigh-level output voltageLow-level output voltageHighimpedanceoffstateoutputcurrentHigh-impedance off-state output currentHigh-level input current, control inputsLow-level input current, control inputsAnalog channel on-state input current during sampleggcycleOperating supply currentSupply and reference currentInputcapacitanceInput capacitanceAnalog inputsControl inputsTEST CONDITIONSVCC = 4.75 V,VCC = 4.75 V,VO = VCC,VO = 0,VI = VCCVI = 0Analog input at VCCAnalog input at 0 VCS at 0 VVref+ = VCCIOH = –360 µAIOL = 3.2 mACS at VCCCS at VCC0.005–0.0050.4–0.41.81.975MIN2.40.410–102.5–2.51–12.535515TYP†MAXUNITVVµAµAµAµAmAmApFoperating characteristics over recommended operating free-air temperature range, VCC = Vref+ = 4.75 V to 5.5 V, fclock(I/O) = 2.048 MHz for TLC548 or 1.1 MHz for TLC549 (unless otherwise noted)PARAMETERELEZSEFStconvLinearity errorZero-scale errorFull-scale errorTotal unadjusted errorConversion timeTotal access and conversion timetatvtdtentdistr(bus)Channel acquisition time (sample cycle)Time output data remainsvalid after I/O CLOCK↓Delay time to data output validOutput enable timeOutput disable timeData bus rise timeSee Figure 1I/O CLOCK↓TESTCONDITIONSTEST CONDITIONSSee Note 6See Note 7See Note 7See Note 8See Operating SequenceSee Operating SequenceSee Operating Sequence812TLC548MINTYP†MAX±0.5±0.5±0.5±0.5172241219TLC549MINTYP†MAX±0.5±0.5±0.5±0.517254UNITLSBLSBLSBLSBµsµsI/Oclockcyclesns4001.4150300nsµsnsns102001.415030010tf(bus)Data bus fall time300300ns†All typicals are at VCC = 5 V, TA = 25°C.NOTES:6.Linearity error is the deviation from the best straight line through the A/D transfer characteristics.7.Zero-scale error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the differencebetween 11111111 and the converted output for full-scale input voltage.8.Total unadjusted error is the sum of linearity, zero-scale, and full-scale errors.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•5元器件交易网www.cecb2b.comSLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 1996TLC548C, TLC548I, TLC549C, TLC549I8-BIT ANALOG-TO-DIGITAL CONVERTERSWITH SERIAL CONTROLPARAMETER MEASUREMENT INFORMATION1.4 VVCC 3 kΩTestPointOutputUnder TestCL(see Note A)See Note BLOAD CIRCUIT FORtd, tr, AND tfLOAD CIRCUIT FORtPZH AND tPHZTestPoint3 kΩOutputUnder TestCL(see Note A)3 kΩTestPointOutputUnder TestCL(see Note A)See Note BLOAD CIRCUIT FORtPZL AND tPLZVCCCS50%tPZLOutput Waveform 1(see Note C)tPZHOutput Waveform 2(see Note C)50%tPHZ50%See Note BVOLTAGE WAVEFORMS FOR ENABLE AND DISABLE TIMES90%VOH0 V50%0 VtPLZ10%VCC0 VI/O CLOCKtdDATA OUT0.8 VOutput2.4 V0.4 V2.4 V0.8 Vtr(bus)tf(bus)VOLTAGE WAVEFORMS FOR RISE AND FALL TIMESVOLTAGE WAVEFORMS FOR DELAY TIMENOTES:A.CL = 50 pF for TLC548 and 100 pF for TLC549; CL includes jig capacitance.B.ten = tPZH or tPZL, tdis = tPHZ or tPLZ.C.Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.Figure 1. Load Circuits and Voltage Waveforms6POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com TLC548C, TLC548I, TLC549C, TLC549I8-BIT ANALOG-TO-DIGITAL CONVERTERSWITH SERIAL CONTROLSLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 1996APPLICATIONS INFORMATIONsimplified analog input analysisUsing the equivalent circuit in Figure 2, the time required to charge the analog input capacitance from 0 to VSwithin 1/2 LSB can be derived as follows:The capacitance charging voltage is given byVC = VS 1–ewhereRt = Rs + riThe final voltage to 1/2 LSB is given byVC (1/2 LSB) = VS – (VS/512)Equating equation 1 to equation 2 and solving for time tc givesVS –(VS/512) = VS 1–eandtc (1/2 LSB) = Rt × Ci × ln(512) Therefore, with the values given the time for the analog input signal to settle istc (1/2 LSB) = (Rs + 1 kΩ) × 60 pF × ln(512) This time must be less than the converter sample time shown in the timing diagrams.Driving Source†RsVSri1 kΩ MAXVCCi55 pF MAXTLC548/9–tc/RtCi( )(1)(2)–tc/RtCi( )(3)(4)(5)VIVI= Input Voltage at ANALOG INVS= External Driving Source VoltageRs= Source Resistanceri= Input ResistanceCi= Input Capacitance†Driving source requirements:•Noise and distortion for the source must be equivalent to the resolution of the converter.•Rs must be real at the input frequency.Figure 2. Equivalent Input Circuit Including the Driving SourcePOST OFFICE BOX 655303 DALLAS, TEXAS 75265•7元器件交易网www.cecb2b.comSLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 1996TLC548C, TLC548I, TLC549C, TLC549I8-BIT ANALOG-TO-DIGITAL CONVERTERSWITH SERIAL CONTROLPRINCIPLES OF OPERATION The TLC548 and TLC549 are each complete data acquisition systems on a single chip. Each contains an internalsystem clock, sample-and-hold function, 8-bit A/D converter, data register, and control logic circuitry. For flexibilityand access speed, there are two control inputs: I/O CLOCK and chip select (CS). These control inputs and aTTL-compatible 3-state output facilitate serial communications with a microprocessor or minicomputer. A conversioncan be completed in 17 µs or less, while complete input-conversion-output cycles can be repeated in 22 µs for theTLC548 and in 25 µs for the TLC549.The internal system clock and I/O CLOCK are used independently and do not require any special speed or phaserelationships between them. This independence simplifies the hardware and software control tasks for the device.Due to this independence and the internal generation of the system clock, the control hardware and software needonly be concerned with reading the previous conversion result and starting the conversion by using the I/O clock. Inthis manner, the internal system clock drives the “conversion crunching” circuitry so that the control hardware andsoftware need not be concerned with this task.When CS is high, DATA OUT is in a high-impedance condition and I/O CLOCK is disabled. This CS control functionallows I/O CLOCK to share the same control logic point with its counterpart terminal when additional TLC548 andTLC549 devices are used. This also serves to minimize the required control logic terminals when using multipleTLC548 and TLC549 devices.The control sequence has been designed to minimize the time and effort required to initiate conversion and obtainthe conversion result. A normal control sequence is:1.CS is brought low. To minimize errors caused by noise at CS, the internal circuitry waits for two rising edgesand then a falling edge of the internal system clock after a CS↓ before the transition is recognized. However,upon a CS rising edge, DATA OUT goes to a high-impedance state within the specified tdis even though therest of the integrated circuitry does not recognize the transition until the specified tsu(CS) has elapsed. Thistechnique protects the device against noise when used in a noisy environment. The most significant bit (MSB)of the previous conversion result initially appears on DATA OUT when CS goes low.2.The falling edges of the first four I/O CLOCK cycles shift out the second, third, fourth, and fifth most significantbits of the previous conversion result. The on-chip sample-and-hold function begins sampling the analoginput after the fourth high-to-low transition of I/O CLOCK. The sampling operation basically involves thecharging of internal capacitors to the level of the analog input voltage.3.Three more I/O CLOCK cycles are then applied to the I/O CLOCK terminal and the sixth, seventh, and eighthconversion bits are shifted out on the falling edges of these clock cycles.4.The final (the eighth) clock cycle is applied to I/O CLOCK. The on-chip sample-and-hold function begins thehold operation upon the high-to-low transition of this clock cycle. The hold function continues for the next fourinternal system clock cycles, after which the holding function terminates and the conversion is performedduring the next 32 system clock cycles, giving a total of 36 cycles. After the eighth I/O CLOCK cycle, CS mustgo high or the I/O clock must remain low for at least 36 internal system clock cycles to allow for the completionof the hold and conversion functions. CS can be kept low during periods of multiple conversion. Whenkeeping CS low during periods of multiple conversion, special care must be exercised to prevent noiseglitches on the I/O CLOCK line. If glitches occur on I/O CLOCK, the I/O sequence between themicroprocessor/controller and the device loses synchronization. When CS is taken high, it must remain highuntil the end of conversion. Otherwise, a valid high-to-low transition of CS causes a reset condition, whichaborts the conversion in progress.A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps 1 through4 before the 36 internal system clock cycles occur. Such action yields the conversion result of the previous conversionand not the ongoing conversion.8POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com TLC548C, TLC548I, TLC549C, TLC549I8-BIT ANALOG-TO-DIGITAL CONVERTERSWITH SERIAL CONTROLSLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 1996PRINCIPLES OF OPERATIONFor certain applications, such as strobing applications, it is necessary to start conversion at a specific point in time.This device accommodates these applications. Although the on-chip sample-and-hold function begins samplingupon the high-to-low transition of the fourth I/O CLOCK cycle, the hold function does not begin until the high-to-lowtransition of the eighth I/O CLOCK cycle, which should occur at the moment when the analog signal must beconverted. The TLC548 and TLC549 continue sampling the analog input until the high-to-low transition of the eighthI/O CLOCK pulse. The control circuitry or software then immediately lowers I/O CLOCK and starts the holding functionto hold the analog signal at the desired point in time and starts the conversion.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•9元器件交易网www.cecb2b.com
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PACKAGINGINFORMATION
OrderableDevice
TLC548CDTLC548CDRTLC548CPTLC548IDTLC548IDRTLC548IPTLC549CDTLC549CDRTLC549CPTLC549IDTLC549IDRTLC549IPTLC549IPSTLC549IPSRTLC549MP
(1)
Status(1)ACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEOBSOLETE
PackageTypeSOICSOICPDIPSOICSOICPDIPSOICSOICPDIPSOICSOICPDIPSOSOPDIP
PackageDrawing
DDPDDPDDPDDPPSPSP
PinsPackageEcoPlan(2)
Qty888888888888888
75250050752500507525005075250050802000
Pb-Free(RoHS)Pb-Free(RoHS)Pb-Free(RoHS)Pb-Free(RoHS)Pb-Free(RoHS)Pb-Free(RoHS)Pb-Free(RoHS)Pb-Free(RoHS)Pb-Free(RoHS)Pb-Free(RoHS)Pb-Free(RoHS)Pb-Free(RoHS)NoneNoneNone
Lead/BallFinishCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCallTI
MSLPeakTemp(3)Level-2-260C-1YEAR/Level-1-220C-UNLIMLevel-2-260C-1YEAR/Level-1-220C-UNLIMLevel-NC-NC-NCLevel-2-260C-1YEAR/Level-1-220C-UNLIMLevel-2-260C-1YEAR/Level-1-220C-UNLIMLevel-NC-NC-NCLevel-2-260C-1YEAR/Level-1-220C-UNLIMLevel-2-260C-1YEAR/Level-1-220C-UNLIMLevel-NC-NC-NCLevel-2-260C-1YEAR/Level-1-220C-UNLIMLevel-2-260C-1YEAR/Level-1-220C-UNLIMLevel-NC-NC-NCLevel-1-220C-UNLIMLevel-1-220C-UNLIMCallTI
Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable.OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)
EcoPlan-Maynotbecurrentlyavailable-pleasecheckhttp://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.
None:NotyetavailableLead(Pb-Free).
Pb-Free(RoHS):TI'sterms\"Lead-Free\"or\"Pb-Free\"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.
Green(RoHS&noSb/Br):TIdefines\"Green\"tomean\"Pb-Free\"andinaddition,usespackagematerialsthatdonotcontainhalogens,includingbromine(Br)orantimony(Sb)above0.1%oftotalproductweight.
(3)
MSL,PeakTemp.--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.TIbasesitsknowledgeandbeliefoninformationprovidedbythirdparties,andmakesnorepresentationorwarrantyastotheaccuracyofsuchinformation.Effortsareunderwaytobetterintegrateinformationfromthirdparties.TIhastakenandcontinuestotakereasonablestepstoproviderepresentativeandaccurateinformationbutmaynothaveconducteddestructivetestingorchemicalanalysisonincomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimited
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