Analysis of Practical X-Compact Designs Subhasish Mitra*, Kee Sup Kim and Shyam Kallepalli Intel Corporation Email: subhasish.mitra@intel.com * -- Contact Author and designated presenter ABSTRACT The theory behind the design of combinational circuits to compact scan chain responses (also called X-Compactor circuits) was described in one of our previous papers. This paper presents an analysis to estimate the expected number of defective chips that may escape detection due to the presence of the X-Compactor circuits. With the help of practical design data it is shown that the impact on the product DPM due to the presence of the X-Compactor is negligible for all practical purposes. A very simple extension to the basic X-Compact approach provides exponential reduction in test response data volume for all practical purposes without any impact on DPM. 1 15-Oct-2002 1. INTRODUCTION For ICs with scan-based Design-for-Testability (DFT) support, some of the major contributors to test cost are: (1) available tester memory; (2) available number of tester channels, (3) test time, and (4) number of pins available for scan-in and scan-out purposes. The X-Compact approach to reducing the test cost, introduced in [Mitra 02a], is shown in Fig. 1.1. Scan In 1 Scan In 2 Scan In n Scan Out 1 Scan Out 2 X-Compactor Scan Out n Out 1 Out m Figure 1.1. Scan Architecture with X-Compact The X-Compactor circuit is a combinational logic network used to reduce the number of scan-out pins almost exponentially. For example, for a design with 400 scan chains we need 11 outputs. This helps in significantly reducing the number of scan pins, the number of scan channels, scan test data volume (since response data volume and mask data volume are reduced exponentially), scan test time (since more scan chains can be supported) and improving test quality (making room to apply higher coverage test patterns). The systematic technique for designing the X-compactor circuits is called X-compact. The X-compact technique does not compromise the error detection and diagnosis capability of scan for all practical purposes even in the presence of unknown logic values (often referred to as X-values). The X-compact technique is non-intrusive, independent of the test patterns used to test the circuit and does not change the system logic and hence, doesn’t affect the circuit performance. Insertion of X-compact circuits does not require any major change to the Automatic Test Pattern Generation (ATPG) flow. The X-compactor logic has very little hardware overhead and can be easily 2 15-Oct-2002 inserted after scan-chain insertion is done. The failing flip-flop in the scan chains can be directly identified from the outputs of the X-Compactor circuit without configuring the chip into a special diagnosis mode. The X-Compact technique is also applicable in a logic Built-In-Self-Test (BIST) environment with and in situations where the number of scan-ins are also reduced using approaches such as those presented in [Hamzaoglu 99, Khoche 02, Koenemann 01, Mitra 02b, Rajski 02, Volkerink 02]. One of the major advantages of an X-Compactor design is its X-tolerance capability and its ability to identify the failing flip-flops for all practical purposes. The X-Compact design technique allows systematic design of response compactors with minimum number of outputs that guarantee error detection when any m or fewer scan chains produce X’s simultaneously at the same scan-out cycle; here, m is a design parameter [Mitra 02c]. Definitely, the larger the value of the parameter m, more X-Compactor outputs are required. In the limiting situation, if m+1 is equal to the number of scan chains, then there will be no reduction in the number of outputs to be observed on the tester. As demonstrated in this paper, the value of m doesn’t have to be more than 1 for practical designs. However, there is a chance that a defect may produce error at a scan-out cycle when two or more scan chains produce Xs simultaneously. In that situation there is no guarantee that the error will be detected and, as a result, there is a finite probability that a defective chip may escape detection. As observed in [Mitra 02a], one way to resolve this problem is by serially scanning out the scan chain contents for the scan-out cycles for which two or more scan chains produce more Xs simultaneously. In this paper, we perform a very thorough analysis of X-Compactor circuits to show that even this serial mode isn’t always necessary. In [Mitra 02a] we found from tester data that the presence of X-Compactor circuits didn’t cause a chip to escape detection. Our analysis in this paper demonstrates that the number of test escapes due to the X-Compactor circuitry will be insignificant, less than 1 DPM, for practical circuits. Section 2 presents an overview of the X-Compact technique. In Sec. 3, we analyze the coverage of errors in the presence of multiple X’s for X-Compactor designs with guaranteed detection capabilities in the presence of a single X. Section 4 presents the distribution of X’s in actual designs and analyzes the DPM impact and test data volume and test time reduction obtained for these designs. Finally, we conclude in Sec. 5. 3 15-Oct-2002 2. OVERVIEW OF X-COMPACT The X-Compactor circuit block shown in Fig. 1.1 is a combinational circuit made up of exclusive-or (XOR) gates. Let us suppose that we have a design with n scan chains. Hence, the X-compactor circuit will have n inputs. Suppose that the X-Compactor has m outputs. The X-Compactor circuit can be represented as a binary matrix (matrix with only 0s and 1s) with n rows and m columns; this matrix is called the X-Compact matrix. Each row of the X-Compactor matrix corresponds to a scan chain and each column corresponds to an X-Compactor output. The entry in row i and column j of the matrix is 1 if and only if the jth X-Compactor output depends on the ith scan chain output; the matrix entry is 0 otherwise. The outputs of all scan chains that an X-Compactor output depends on are XOR-ed together to produce that particular X-Compact output. 111111001100011010101001 0101001110110111Figure 2.1. X-Compact matrix for the X-Compactor Circuit of Fig. 2.2. Scan Scan Scan Scan Out 1 Out 2 Out 3 Out 4 Scan Out 5 Scan Scan Out 6 Out 7 Scan Out 8 XOR XOR XOR Out 1 XOR XOR XOR Out 2 XOR XOR XOR Out 3 XOR XOR XOR Out 4 XOR XOR XOR Out 5 Figure 2.2. An example X-Compactor Circuit. Figure 2.1 shows the X-Compact matrix for the X-Compactor circuit of Fig. 2.2. The X-Compactor circuit of Fig. 2.2 has 8 inputs and 5 outputs. The first output is obtained by XOR-4 15-Oct-2002 ing the outputs of scan chains 1, 2, 3, 4, and 5; hence, the first column of the X-Compact matrix has 1s in the first five rows. The following property of X-Compactor circuits was proved in [Mitra 02a]. Suppose that we want the following error detection capability of X-Compact circuits: 1. When a single scan chain produces an error and no scan chain produces X at any scan-out cycle, at least one of the X-Compactor outputs must be erroneous; 2. When 2 scan chains simultaneously produce errors and no scan chain produces X at any scan-out cycle, at least one of the X-Compactor outputs must be erroneous; 3. When 3 scan chains simultaneously produce errors and no scan chain produces X at any scan-out cycle, at least one of the X-Compactor outputs must be erroneous; 4. When any odd number of scan chains simultaneously produce errors and no scan chain produces X at any scan-out cycle, at least one of the X-Compactor outputs must be erroneous; 5. When a scan chain produces error and another single scan chain produces X simultaneously at any scan-out cycle, at least one of the X-Compactor outputs must be erroneous. It was shown in [Mitra 02a] that the above capabilities are satisfied by any X-Compactor circuit whose X-Compact matrix has the following properties: 1. Every row is distinct; 2. Every row has an equal number of 1s; 3. Every row has an odd number of 1s. Table 2.1 shows an exponential reduction in the number of X-Compact outputs thus obtained. The reader can refer to [Mitra 02c] for generating X-Compactor designs with guaranteed error detection when 2 or more scan chains simultaneously produce Xs at any scan-out cycle. 5 15-Oct-2002 Table 2.1. Relationship between number of scan chains and X-Compact outputs with guaranteed detection of 1, 2, 3 or odd number of simultaneous scan failures and scan failures in the presence of an X at the same scan-out cycle. Number of scan Chains 5-10 11-20 21-35 36-56 57-126 127-252 253-462 463-792 793-1,716 1,717-3,432 Minimum number of X-Compact outputs 5 6 7 8 9 10 11 12 13 14 Reduction 2x 3x 5x 7x 14x 25x 42x 66x 130x 240x 3. ERROR DETECTION COVERAGE OF X-COMPACT IN THE PRESENCE OF MULTIPLE X’S The X-Compactor designs discussed in Sec. 2 guarantee detection of an error when a scan chain produces error and another scan chain produces X at the same scan-out cycle. This doesn’t necessarily mean when a scan chain produces error and two or three scan chains produce X’s simultaneously at the same scan-out cycle that error will not be detected. It really depends on which scan chain produced the error and which scan chains produced 2 or 3 X’s. In this section, we present analytical expressions for the probability that an error will not be detected when 2 or 3 (or more) scan chains produce X’s simultaneously at the same scan-out cycle. The analysis will be done for X-Compact designs when the number of 1s in each row of the X-Compact matrix is 3 because that’s sufficient for the practical designs illustrated later in this paper. The analysis can be extended for any number of 1s in each row of the X-Compact matrix. X-Compact matrices with 3 1s in every row can be designed in two different ways: 1. Generate rows so that every row has 2 1s; finally, add one extra column with 1s in every row. This design will be referred to as an X-Compactor of Type 1 in this paper. For designs with n X-Compactor outputs, the probability that an error produced by a scan will not be detected when k other scan chains produce Xs simultaneously at the 6 15-Oct-2002 same scan-out cycle is denoted by p(n, k, 2). It is assumed that at any scan-out cycle there is an equal chance that any scan chain will produce an X. Note that, this is a pessimistic assumption. 2. Generate rows so that every row has 3 1s. This design will be referred to as an X-Compactor of Type 2 in this paper. For designs with n X-Compactor outputs, the probability that an error produced by a scan will not be detected when k other scan chains produce Xs simultaneously at the same scan-out cycle is denoted by p(n, k, 3). It is assumed that at any scan-out cycle there is an equal chance that any scan chain will produce an X. Note that, this is a pessimistic assumption. Tables 3.1-3.2 show the values of p(n, k, 2), and p(n, k, 3) for various values of n and k. The derivations of the closed forms of these expressions are given in Appendix 1. Table 3.1. p(n, k, 2) for various values of n and k. n = No. of X-Compactor Outputs 13 15 17 19 21 23 25 27 29 31 33 35 N = Max. no. of Scan chains 66 91 120 153 190 231 276 325 378 435 496 561 k = 2 p(n, 2, 2) 4.8% 3.6% 2.8% 2.2% 1.8% 1.5% 1.2% 1.1% 0.9% 0.8% 0.7% 0.6% k = 3 p(n, 3, 2) 10% 9.4% 7.4% 6% 4.9% 4.1% 3.5% 3% 2.6% 2.3% 2% 1.8% 7 15-Oct-2002 Table 3.2. p(n, k, 3) for various values of n and k. n = No. of X-Compactor Outputs 12 14 16 18 20 N = Max. no. of Scan chains 220 364 560 816 1,140 k = 2 p(n, 2, 3) 5% 3% 2% 1.6% 1.2% k = 3 p(n, 3, 3) 15% 10% 7% 5% 4% Let Y be the yield of the part. (1-Y) is the proportion of parts that are defective. If C is the proportion of defective chips detected by the regular scan test, the number of defective chips that will escape is (1-Y)(1-C) and the resulting customer DPM is (1Y)(1C)106. Y(1Y)(1C)Suppose that this DPM value is 100 DPM and the yield Y is 80%. This means, the value of C must be 0.9995999; i.e., 1-C is approximately 400 per million; i.e., 19.9919991% of all manufactured chips must be detected when defective chips constitute 20% of all manufactured chips. If z is the proportion of detected defective chips cannot be detected due to the presence of the X-Compactor, then the resulting DPM is (1Y)(1C)(1Y)Cz106. For Y(1Y)(1C)(1Y)Cz80% yield and a test quality of 100 DPM without X-Compactor, the DPM is 0.000080020.1999198z106. 0.800080020.1999198z 4. X-DISTRIBUTION IN ACTUAL DESIGNS In this section we present data about the distribution of X’s out of the scan chains in industrial designs. This data is also referred to as “X-density” in the industry. For each design we report the number of scan-out cycles producing no X’s, the number of scan-out cycles producing 1 X, the number of scan-out cycles producing 2 X’s, and so on. 4.1. DESIGN 1 WITH MODERATE X-MANAGEMENT Table 4.1 shows the example of Design1 where 86% of all scan-out cycles (the total number of scan-out cycles is equal to the product of the total number of test patterns and the length of the 8 15-Oct-2002 longest scan chain) don’t produce any X’s. For this design, we describe three different X-Compactor designs in Sec. 4.1.1, 4.1.2 and 4.1.3. Table 4.1. Distribution of Xs for Design1 No. of Xs 0 1 2 3 4 5 or more No. of scan-out cycles 1,082,546 157,791 17,927 1,566 170 0 % of scan-out cycles 85.91% 12.53% 1.422% 0.1243% 0.0135% 0% 4.1.1. X-COMPACTOR-1 For design 1 with 400 scan chains and 31 scan outputs, we can use an X-Compactor of Type 1. We refer to this configuration as X-Compactor-1. Since the X-Compactor design guarantees error detection in the presence of a single X, detection of a defective chip is guaranteed for (85.91 + 12.53)% = 98.44% of scan-out cycles. These are the scan-out cycles producing no X or a single X. From Table 3.1, with X-Compactor-1, a defective chip implementing Design1 will not be detected if the defective chip produces error in 0.8% of the scan-out cycles producing 2 Xs, 2.3% of the scan-out cycles producing 3 Xs and 3.7% of scan-out cycles producing 4 Xs. Thus an error produced by a defect in a scan-out cycle will not be detected for 0.0144% of all cases. It is realistic to assume that a defect will produce error for at least 2 scan-out cycles as demonstrated by tester data [ELF35]. Thus, the probability that a defective chip will not be detected due to the presence of the X-Compactor but will otherwise be detected in 20.0144the absence of the X-Compactor is = 0.000002%. Thus, the impact on DPM is less 100than 0.02 DPM. Suppose that a defect produces error in scan-out cycles c1 and c2. In the above analysis it was assumed that there is no correlation between how X’s and errors appear in the two scan-out cycles c1 and c2. Thus, the event that an error will not be detected in cycle c1 is independent of 9 15-Oct-2002 the event that an error will not be detected in c2. Table 4.2 models this correlation by choosing a number n between 1 and 2 and raises 0.0144% to the power of n to obtain the percentage of defective chips not detected due to the presence of the X-Compactor. In the worst-case n = 1 which implies that if the error is not detected in c1, it will not be detected in c2 too. This situation is very unlikely but still covered for completeness. If the original test quality achieved is 100 DPM without X-Compactor and the yield is 80%, the overall DPM with X-Compactor is calculated in Table 4.2. If the DPM impact is unacceptable then the user has to use the serial mode for the cycles in which 2 or more X’s are produced in order to guarantee no impact on DPM (Sec. 4.1.3). For test quality of more than 100 DPM, the impact of the X-Compactor will be lower. Table 4.2. n vs. DPM for X-Compactor-1. N 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 % defective chips undetected due to X-Compactor (z) 0.0144 0.006 0.0025 0.0010 0.0004 0.0002 0.00007 0.00003 0.00001 0.000005 0.000002 DPM with X-Compact 135 115 106 102 101 100.5 ~ 100 ~ 100 ~ 100 ~ 100 ~ 100 DPM without X-Compact 100 100 100 100 100 100 100 100 100 100 100 4.1.2. X-COMPACTOR-2 For design 1 with 400 scan chains an X-Compactor of Type 2 with 20 outputs can also be used. In this scenario, a defect will not be detected if it produces error in 1.2% of the cycles producing 2 Xs and 4% of the cycles producing 3 Xs (Table 3.1). Thus, the probability that an error created by a defect in a scan-out cycle will not be detected in that scan-out cycle but will otherwise be detected in the absence of the X-Compactor is 0.036%. Even if we pessimistically assume that a defect creates error in 2 scan-out cycles, the impact on DPM will 10 15-Oct-2002 be less than 0.13 DPM. This analysis assumes that there is no correlation between how X’s and errors appear in the two scan-out cycles. Table 4.3 models this correlation by choosing a number n between 1 and 2 and raises 0.036% to the power of n. The original test quality is 100 DPM without X-Compactor and the yield is 80% and the overall DPM with X-Compactor is shown in Table 4.3. If the DPM impact due to the correlation is unacceptable, then the user has to use the X-Compact technique with serial support (Sec. 4.1.3). For test quality of more than 100 DPM, the impact of the X-Compactor will be lower. Table 4.3. n vs. DPM for X-Compactor-2. N 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 % defective chips undetected due to X-Compactor (z) 0.036 0.0163 0.0073 0.0033 0.0015 0.0007 0.0003 1.4 0.6 0.3 0.13 DPM with X-Compact 189 141 118 107 103 101 100.5 ~ 100 ~ 100 ~ 100 ~ 100 DPM without X-Compact 100 100 100 100 100 100 100 100 100 100 100 4.1.3. X-COMPACTOR-3 A third approach is to design an X-Compactor with 1 X tolerance with 11 outputs (or more) and to serially scan out the contents of all the 400 scan chains out of 11 outputs in 37 cycles (or less) only for those scan-out cycles in which the number of X’s in a scan-out cycle is greater than 1 (i.e., 3% of the cycles). This approach guarantees no impact on DPM but the average number of scan-out cycles is roughly 1.5%3798.5%1 = 1.54 compared to 37 if there was no X-Compactor (i.e., only 11 scan chains). Thus, we obtain 24 times reduction in test time. Also, the amount of test response data will be on an average equal to 1.5%40098.5%11 = 11 15-Oct-2002 16.835 bits per scan-out cycle instead of 400 which gives approximately 24 times reduction in test response data compared to when no X-Compactor is used. Note that, there is no loss of DPM in this case. 4.2. DESIGN 2 WITH WELL-MANAGED X’S Table 4.4 shows the example of a design (Design 2) where more than 98% of all scan-out cycles (the total number of scan-out cycles is equal to the product of the total number of test patterns and the length of the longest scan chain) don’t produce any X’s. For this design, we describe three different X-Compact designs in Sec. 4.2.1, 4.2.2 and 4.2.3. Table 4.4. Distribution of Xs for Design2 with well-managed X’s No. of Xs 0 1 2 3 4 5 6 7 8, 9, 10, 11 12 13 or more No. of scan-out cycles 539,027 5,024 2,674 620 0 139 80 23 0 1 0 % of scan-out cycles 98.43% 0.93% 0.49% 0.11% 0% 0.025% 0.015% 0.004% 0% 0.0002% 0% 4.2.1. X-COMPACTOR-4 For design 2 with 400 scan chains we use an X-Compactor of Type 1 with 31 outputs. Following an analysis similar to Sec. 4.1.1, detection of a defective chip is guaranteed for (98.43 + 0.93)% = 99.36% of scan-out cycles. These are the scan-out cycles producing no X or a single X. For an X-Compactor design of Type-1 with 400 scan chains and 31 scan outputs, a defective chip implementing Design2 will not be detected for 0.8% of the scan-out cycles producing 2 Xs and 2.8% of the scan-out cycles producing 3 Xs. It is pessimistically assumed 12 15-Oct-2002 that errors produced on scan-out cycles producing 5 or more Xs will not be detected. Thus, a defective chip will not be detected if the defect produces error in one of the 0.04% of the scan-out cycles. Even if we pessimistically assume that a defect produces error in two scan-out 0.04cycles, the impact on DPM will be less than 1002 = 0.16 DPM. This analysis assumes that there is no correlation between how X’s and errors appear in the two scan-out cycles. Similar to Sec. 4.1.1 and 4.1.2, Table 4.5 models this correlation by choosing a number n between 1 and 2 and raises 0.04% to the power of n. The corresponding DPM assuming 80% yield and test quality of 100 DPM without X-Compactor is also shown in Table 4.5. If the DPM impact due to the correlation is unacceptable, then the user has to use the X-Compact technique with serial support (Sec. 4.2.3). For test quality of more than 100 DPM, the DPM impact of the X-Compactor will be lower. Table 4.5. n vs. DPM for X-Compactor-4. n 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 % defective chips undetected due to X-Compactor (z) 0.04 0.0183 0.0084 0.0039 0.0018 0.0008 0.0004 0.00017 0.00007 0.00003 0.000016 DPM with X-Compact 199 146 121 109 105 102 101 100.5 ~ 100 ~ 100 ~ 100 DPM without X-Compact 100 100 100 100 100 100 100 100 100 100 100 4.2.2. X-COMPACTOR-5 If we use an X-Compactor of Type 2 with 20 outputs for design 2 with 400 scan chains, a defect will not be detected if it produces error in 1.2% of the cycles producing 2 Xs and 4% of the cycles producing 3 Xs. Thus, the probability that an error created by a defect in a scan-out cycle will not be detected in that scan-out cycle is 0.054%. Here, we pessimistically assumed 13 15-Oct-2002 that for all cycles with 4 or more Xs, the error will not be detected. Even if we pessimistically assume that a defect creates error in 2 scan-out cycles, the impact on DPM will be less than 0.3 DPM. Similar to Table 4.5, Table 4.6 models the correlation between appearance of X’s and errors by choosing a number n between 1 and 2 and raises 0.054% to the power of n. The corresponding DPM assuming 80% yield and test quality of 100 DPM without X-Compactor is also shown in Table 4.6. If the DPM impact due to the correlation is unacceptable, then the user has to use the X-Compact technique with serial support (Sec. 4.2.3). For test quality of more than 100 DPM, the DPM impact of the X-Compactor will be lower. Table 4.6. n vs. DPM for X-Compactor-5. n 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 % defective chips undetected due to X-Compactor (z) 0.054 0.0234 0.0109 0.0051 0.0024 0.0011 0.0005 0.0002 0.00001 0.00005 0.00003 DPM with X-Compact 233 158 127 112 106 102 101 100.5 ~ 100 ~ 100 ~ 100 DPM without X-Compact 100 100 100 100 100 100 100 100 100 100 100 4.2.3. X-COMPACTOR-6 Another approach is to design an X-Compactor with 1 X tolerance with 11 outputs (or more) and to serially scan out the contents of all the 400 scan chains out of 11 outputs in 37 cycles (or less) at the scan-out cycles for which the number of X’s in a scan-out cycle is greater than 1 (i.e., 0.64% of the cycles). This approach guarantees no impact on DPM but the average number of scan-out cycles is roughly 0.64%3799.36%1 = 1.23 compared to 37 if there was no X-Compactor (i.e., only 11 scan chains). Thus, we obtain 30 times reduction in test 14 15-Oct-2002 time. Also, the amount of test response data will be on an average equal to 0.64%40099.36%11 = 13.48 bits per scan-out cycle instead of 400 which gives approximately 30 times reduction in test response data compared to when no X-Compactor is used. This huge reduction comes without any loss of DPM. 4.3. DESIGN 3 WITH ILL-MANAGED X’S Table 4.7 shows the example of Design3 where only 73.8% of all scan-out cycles don’t produce any X’s. This is an example where X-management isn’t well-managed. For this design, we describe three different X-Compactor designs in Sec. 4.3.1, 4.3.2 and 4.3.3. Table 4.7. Distribution of Xs for Design3 with ill-managed X’s No. of Xs 0 1 2 3 4 5 or more No. of scan-out cycles 92,968 27,703 4,672 595 61 1 % of scan-out cycles 73.8% 22% 3.6% 0.47% 0.048% 0.007% 4.3.1. X-COMPACTOR-7 For design 3 with 400 scan chains we use an X-Compactor of Type 1 with 31 outputs. Following an analysis similar to Sec. 4.1.1, detection of a defective chip is guaranteed for (73.8 + 22)% = 95.8% of scan-out cycles. These are the scan-out cycles producing no X or a single X. For an X-Compactor design of Type-1 with 400 scan chains and 31 scan outputs, a defective chip implementing Design2 will not be detected for 0.8% of the scan-out cycles producing 2 Xs and 2.8% of the scan-out cycles producing 3 Xs. It is pessimistically assumed that errors produced in scan-out cycles producing 4 or more Xs will not be detected. Thus, a defective chip will not be detected if the defect produces error in one of the 0.088% of the scan-out cycles. Even if we pessimistically assume that a defect produces error in two scan-out 15 15-Oct-2002 0.088cycles, the impact on DPM will be less than 1002 = 0.77 DPM. This analysis assumes that there is no correlation between how X’s and errors appear in the two scan-out cycles. Similar to Sec. 4.1.1 and 4.1.2, Table 4.8 models this correlation by choosing a number n between 1 and 2 and raises 0.088% to the power of n. The corresponding DPM assuming 80% yield and test quality of 100 DPM without X-Compactor is also shown in Table 4.8. If the DPM impact due to the correlation is unacceptable, then the user has to use the X-Compact technique with serial support (Sec. 4.3.3). For test quality of more than 100 DPM, the DPM impact of the X-Compactor will be lower. Table 4.8. n vs. DPM for X-Compactor-7. n 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 % defective chips undetected due to X-Compactor (z) 0.088 0.044 0.0215 0.01 0.005 0.0026 0.0013 0.00064 0.00032 0.00016 0.000077 DPM with X-Compact 318 209 154 125 112 106 103 101 100.7 ~ 100 ~ 100 DPM without X-Compact 100 100 100 100 100 100 100 100 100 100 100 4.3.2. X-COMPACTOR-8 If we use an X-Compactor of Type 2 with 20 outputs for design 2 with 400 scan chains, a defect will not be detected if it produces error in 1.2% of the cycles producing 2 Xs and 4% of the cycles producing 3 Xs. Thus, the probability that an error created by a defect in a scan-out cycle will not be detected in that scan-out cycle is 0.12%. Here, we pessimistically assumed that for all cycles with 4 or more Xs, the error will not be detected. Even if we pessimistically assume that a defect creates error in 2 scan-out cycles, the impact on DPM will be less than 1 DPM. Similar to Table 4.6, Table 4.9 models the correlation between appearance of X’s and 16 15-Oct-2002 errors by choosing a number n between 1 and 2 and raises 0.12% to the power of n. The corresponding DPM assuming 80% yield and test quality of 100 DPM without X-Compactor is also shown in Table 4.6. If the DPM impact due to the correlation is unacceptable, then the user has to use the X-Compact technique with serial support (Sec. 4.3.3). For test quality of more than 100 DPM, the DPM impact of the X-Compactor will be lower. Table 4.6. n vs. DPM for X-Compactor-8. n 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 % defective chips undetected due to X-Compactor (z) 0.12 0.06 0.031 0.016 0.008 0.004 0.0021 0.00108 0.00055 0.00028 0.00014 DPM with X-Compact 398 249 177 140 120 110 105 102 101 100.7 ~ 100 DPM without X-Compact 100 100 100 100 100 100 100 100 100 100 100 4.2.3. X-COMPACTOR-9 Another approach is to design an X-Compactor with 1 X tolerance with 11 outputs (or more) and to serially scan out the contents of all the 400 scan chains out of 11 outputs in 37 cycles (or less) at the scan-out cycles for which the number of X’s in a scan-out cycle is greater than 1 (i.e., 0.64% of the cycles). This approach guarantees no impact on DPM but the average number of scan-out cycles is roughly 4.2%3795.8%1 = 2.5 compared to 37 if there was no X-Compactor (i.e., only 11 scan chains). Thus, we obtain 14.7 times reduction in test time. Also, the amount of test response data will be on an average equal to 4.2%40095.8%11 = 27.34 bits per scan-out cycle instead of 400 which gives approximately 14.6 times reduction 17 15-Oct-2002 in test response data compared to when no X-Compactor is used. This huge reduction comes without any loss of DPM. 5. CONCLUSIONS This paper clearly shows the usefulness of the X-Compact technique for response compaction purposes. It is demonstrated using data from actual designs that X-Compactor designs with 1 X tolerance are sufficient with almost negligible DPM impact for all practical purposes. It is also shown that X-Compactor designs with 1 X tolerance and serial scan-out capabilities for scan-out cycles with 2 or more X’s enable response data volume reduction and also test time reduction by at least an order of magnitude with no DPM impact, compared to conventional scan, even for designs with ill-managed X’s. 6. REFERENCES [ELF35] Stanford CRC ELF35 Test Chip Experiment, http://crc.stanford.edu [Hamzaoglu 99] Hamzaoglu, I., and J. H. Patel, “Reducing Test Application Time for Full Scan Embedded Cores,” Proc. Intl. Symp. Fault-Tolerant Computing, pp. 260-267, 1999. [Koenemann 01] Koenemann, B., C. Barnhart, B. Keller, T. Snethen, O. Farnsworth and D. Wheater, “A SmartBIST Variant with Guaranteed Encoding,” Proc. IEEE Asian Test Symp., pp. 325-330, 2001. [Khoche 02] Khoche, A., S. Mitra, E. Volkerink and J. Rivoir, “Test Vector Compression using ATE-DFT Synergies,” Proc. IEEE VLSI Test Symp., 2002. [Mitra 02a] Mitra, S., and K.S. Kim, “X-Compact: Efficient Response Compaction for Test Cost Reduction,” Proc. IEEE Intl. Test Conf., 2002. [Mitra 02b] Mitra, S., and K.S. Kim, “XPAND: Efficient Test Stimulus Compaction,” Tech. Report, Intel Corp., 2002. [Mitra 02c] Mitra, S., and K.S. Kim, “X-Compact: Efficient Response Compaction for Test Cost Reduction,” Tech. Report, Intel Corp., 2002. [Rajski 02] Rajski, J., et al., “Embedded Deterministic Test for Low Cost Manufacturing Test,” Proc. IEEE Intl. Test Conf., 2002. [Volkerink 02] Volkerink, E.H., A. Khoche and S. Mitra, “Packet Based Test Vector Compression Techniques,” Proc. IEEE Intl. Test Conf., 2002. 18 15-Oct-2002 APPENDIX 1. First, we derive the expression for p(n, k, 2) for k = 2 and 3. Suppose that scan chain i produces an error. If the remove the X-Compact matrix column with all 1s, then each row of the resulting matrix has two 1s; thus, this error can be propagated to only two X-Compactor outputs, say g and h in addition to the output corresponding to the column of all 1s. For this error to be undetectable in the presence of two scan chains producing Xs, the Xs must be produced by the scan chains that have 1s in columns g and h of the X-Compact matrix. Nn2n2111Thus, p(n, 2, 2) = N33n2, where N = . Similarly, p(n, 3, 2) = Nn2n2n2n2N2n5[211211]1, where N = N44n2. 19 15-Oct-2002