元器件交易网www.cecb2b.com SCDS049C – MARCH 1998 – REVISED MAY 1998SN74CBTD1621020-BIT FET BUS SWITCHWITH LEVEL SHIFTINGD5-Ω Switch Connection Between Two PortsDTTL-Compatible Input LevelsDDesigned to Be Used in Level-ShiftingDApplicationsPackage Options Include Plastic 300-milShrink Small-Outline (DL), Thin ShrinkSmall-Outline (DGG), and Thin VerySmall-Outline (DGV) PackagesDGG, DGV, OR DL PACKAGE(TOP VIEW)descriptionThe SN74CBTD16210 provides 20 bits ofhigh-speed TTL-compatible bus switching. Thelow on-state resistance of the switch allowsconnections to be made with minimal propagationdelay. A diode to VCC is integrated in the circuit toallow for level shifting between 5-V inputs and3.3-V outputs.The device is organized as a dual 10-bit busswitch with separate output-enable (OE) inputs. Itcan be used as two 10-bit bus switches or as one20-bit bus switch. When OE is low, the associated10-bit bus switch is on and A port is connected toB port. When OE is high, the switch is open, anda high-impedance state exists between the ports.The SN74CBTD16210 is characterized foroperation from –40°C to 85°C.NC1A11A21A31A41A51A6GND1A71A81A91A102A12A2VCC2A3GND2A42A52A62A72A82A92A101234567891011121314151617181920212223244847464544434241403938373635343332313029282726251OE2OE1B11B21B31B41B5GND1B61B71B81B91B102B12B22B3GND2B42B52B62B72B82B92B10NC – No internal connectionFUNCTION TABLE(each 10-bit bus switch)INPUTOELHFUNCTIONA port = B portZPlease be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.Copyright © 1998, Texas Instruments IncorporatedPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•1元器件交易网www.cecb2b.comSCDS049C – MARCH 1998 – REVISED MAY 1998SN74CBTD1621020-BIT FET BUS SWITCHWITH LEVEL SHIFTING logic diagram (positive logic)1A12461B11A1012361B101OE482A113352B1252A10242B102OE47absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 VInput voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 VContinuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mAInput clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mAPackage thermal impedance, θJA (see Note 2):DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/WDGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93°C/WDL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94°C/WStorage temperature range, Tstg –65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 150°C†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.NOTES:1.The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.2.The package thermal impedance is calculated in accordance with JESD 51.recommended operating conditions (see Note 3)MINVCCVIHVILTASupply voltageHigh-level control input voltageLow-level control input voltageOperating free-air temperature–404.520.885MAX5.5UNITVVV°CNOTE 3:All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.2POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com SCDS049C – MARCH 1998 – REVISED MAY 1998SN74CBTD1621020-BIT FET BUS SWITCHWITH LEVEL SHIFTINGelectrical characteristics over recommended operating free-air temperature range (unlessotherwise noted)PARAMETERVIKVOHIIICC∆ICC‡CiCio(OFF)ron§VCC = 4.5 V,See Figure 2VCC = 0 V,VCC = 5.5 V,Control inputsControl inputsVCC = 5.5 V,VCC = 5.5 V,VI = 3 V or 0VO = 3 V or 0,VCC = 4.5 VTEST CONDITIONSII = –18 mAVI = 5.5 VVI = 5.5 V or GNDIO = 0,One input at 3.4 V,OE = VCCVI = 0=0VI = 2.4 V,II = 64 mAII = 30 mAII = 15 mAVI = VCC or GNDOther inputs at VCC or GND4.55.555357750ΩMINTYP†MAX–1.210±11.52.5UNITVµAmAmApFpF†All typical values are at VCC = 5 V, TA = 25°C.‡This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.§Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined bythe lowest voltage of the two (A or B) terminals.switching characteristics over recommended operating free-air temperature range, CL = 50 pF(unless otherwise noted) (see Figure 1)PARAMETERtpd¶tenFROM(INPUT)A or BOETO(OUTPUT)B or AA or B1.5MINMAX0.259.8UNITnsnstdisOEA or B1.58.9ns¶The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, whendriven by an ideal voltage source (zero output impedance).POST OFFICE BOX 655303 DALLAS, TEXAS 75265•3元器件交易网www.cecb2b.comSCDS049C – MARCH 1998 – REVISED MAY 1998SN74CBTD1621020-BIT FET BUS SWITCHWITH LEVEL SHIFTING PARAMETER MEASUREMENT INFORMATION7 VFrom OutputUnder TestCL = 50 pF(see Note A)500 ΩS1OpenGND500 ΩOutputControl(low-levelenabling)tPZLOutputWaveform 1S1 at 7 V(see Note B)tPZHVOH1.5 VVOLTAGE WAVEFORMSPROPAGATION DELAY TIMES1.5 VVOLOutputWaveform 2S1 at Open(see Note B)tPLZ1.5 VtPHZ3.5 VVOL + 0.3 VVOLTESTtpdtPLZ/tPZLtPHZ/tPZHS1Open7 VOpen3 V1.5 V1.5 V0 VLOAD CIRCUIT3 VInput1.5 V1.5 V0 VtPLHOutputtPHL1.5 VVOHVOH – 0.3 V0 VVOLTAGE WAVEFORMSENABLE AND DISABLE TIMESNOTES:A.CL includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.D.The outputs are measured one at a time with one transition per measurement.E.tPLZ and tPHZ are the same as tdis.F.tPZL and tPZH are the same as ten.G.tPLH and tPHL are the same as tpd.Figure 1. Load Circuit and Voltage Waveforms4POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com SCDS049C – MARCH 1998 – REVISED MAY 1998SN74CBTD1621020-BIT FET BUS SWITCHWITH LEVEL SHIFTINGTYPICAL CHARACTERISTICSOUTPUT VOLTAGE HIGHvsSUPPLY VOLTAGE43.753.5VOH– Output Voltage High – V3.2532.752.52.2521.751.54.54.7555.255.55.75TA = 85°C–100 µA–6 mA–12 mA–24 mA43.75VOH– Output Voltage High – V3.53.2532.752.52.2521.751.54.54.7555.255.55.75TA = 25°C–100 µA–6 mA–12 mA–24 mAOUTPUT VOLTAGE HIGHvsSUPPLY VOLTAGEVCC – Supply Voltage – VVCC – Supply Voltage – VOUTPUT VOLTAGE HIGHvsSUPPLY VOLTAGE43.753.5VOH– Output Voltage High – V3.2532.752.52.2521.751.54.54.7555.255.55.75TA = 0°C–100 µA–6 mA–12 mA–24 mAVCC – Supply Voltage – VFigure 2. VOH ValuesPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•5元器件交易网www.cecb2b.com
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